1. Field of the Invention
The present invention relates generally to data processing systems, and more particularly to a memory control interface apparatus for use with an external memory device in conjunction with a single-chip microprocessor or a microprocessor based system.
2. Description of the Prior Art
Known microprocessor systems rely on the proper operation of the microprocessor for data transfer to and from an external memory. Typically, a single microprocessor command is employed for enabling an external memory. As a result of microprocessor errors, invalid data can be transferred to the memory so the integrity of the stored data is destroyed.
External memories in the form of dynamic semiconductor memory cells such as dynamic random access memories (RAM) must be refreshed or replenished to periodically place an additional charge on all the memory cells that are at a logic 1 level. In known microprocessor systems, the dynamic RAM is usually refreshed with each read operation of the memory performed by the microprocessor. When the dynamic RAM is not being read to transfer data to the microprocessor, a required processing task of the microprocessor is sequentially reading through the memory to refresh memory at a determined time interval. Such refreshing arrangement adds to the processing overhead and results in inefficiency in the microprocessor system. In addition, the resulting refreshing rate of such arrangements is higher than necessary for maintaining reliable memory operation and as a result increases the power requirements for the dynamic RAM.